1. Field of the Invention:
The present invention relates to multiple-processor computer system architecture. More particularly, the present invention describes the hardware implementation of a bus-to-bus interface over which multiple master devices may communicate with multiple shared slave devices while maintaining data consistency between accessing masters.
2. Art Background:
Multipurpose computer systems generally contain a communications pathway over which the computer may communicate to a variety of internal and external devices. This communications pathway is typically termed a bus, which permits a device within the computer to either talk with or listen to another device also connected to the bus. The communications from one device to another commonly consist of master and slave operations, such as read or write depending whether the device is controlling, or being controlled by another device. In bus communications, a controlling device, generally termed a master, issues a command. Thereafter, a controlled device, commonly termed a slave, will accept the command and issue a completion signal when finished. Some buses permit other forms of acknowledgement, such as the indication of the occurrence of an error. In multiple master computer systems, buses also permit a slave device to signal that the controlling master device should "rerun" or relinquish the bus and retry to access the slave at some later time. A rerun cycle is issued when a slave is presently occupied, and cannot accept a command issued from a master. Where a slave cannot accept a task from a master, the slave will indicate that the master should disconnect from the bus and retry the access at some later time, thereby freeing the bus so that another master may access another slave. A prior art multiple processor is shown in FIG. 1a. Rerun cycles are issued when a slave is engaged in an internal deadlock condition, or when a slave is engaged in a lengthy task or internal access of long duration.
Whenever a rerun cycle is issued, the disconnection of the master from the bus may occur in one of two fashions. If a slave issues a rerun cycle when the slave has accepted an operation from a master, and the slave is engaged in an internal operation or a task of long duration, such a disconnect of the master is termed stateful. That is, after the slave signals the master to disconnect from the bus the slave retains data and conditions on behalf of the disconnected master. In contrast, a stateless disconnect occurs when a slave, for whatever reason, cannot accept an access attempt from a master, before the access triggers any internal operation, at which time the slave issues the rerun command and signals the master to disconnect from the bus. For example, the slave may already be engaged on behalf of another master, or another internal condition may require the slave to retain access to the bus before the slave can accept another task from a master. If a slave cannot accept an access by a master and issues a rerun command, and the slave does not maintain any state or storage of any information that the access ever occurred, then the disconnect is stateless. Stateless disconnects are typically encountered whenever a master attempts to access a slave, but all registers or I/O ports within the slave are presently engaged. In the case of a stateless disconnect, no information or conditions are stored in the slave regarding the access attempt by the master, and the slave remains open to other masters attempting to access a slave. In both circumstances, it is desirable that the master device attempting to access the slave disconnect from the bus so that the bus may be used for other gainful activity pending completion of the slave's task.
In a multiple processor environment, there exists a significant risk that a master, other than the master delegating the task to a particular slave, will access the slave upon completion of the slave's task. In the absence of cautionary measures, it is possible that data or conditions intended for a particular master could be transferred to the first master accessing the slave upon completion of the slave's cycle. To guard against inadvertent transfer of data or conditions from a slave to an erroneous master, prior art single bus multiple processor architectures provide that the slave device can discriminate between access attempts by the various masters operating on the bus. Thus, a slave can identify from which master it is disconnected, and will permit only that master to reconnect to it when the delegated task is completed. As a result, until the slave device completes its tasks and transfers the desired information or conditions to the master assigning the task, all other master access attempts will be rejected, and the master attempting the access will be instructed to rerun. Typically the discrimination information which permits a slave to distinguish between masters is contained and maintained within the slave device itself. FIGS. 1b and 1c illustrate prior art master and slave devices containing self identification and discrimination facilities.
More recently, multiple bus architectures operating within multiple processor system environments have become common. In multiple bus multiple processor systems, not all slave devices operating on one bus of the system may have the ability to discriminate between master devices which operate on that, or another bus. If the slave device itself possesses no facility for ensuring consistency between data stored in the slave and the master for which the data is intended, the transfer of data on that bus may be compromised. The consistency between data and intended master is generally termed coherence. In such systems, the likelihood of data incoherence, that is the inadvertent data transfer from slave to master, is increased dramatically whenever a slave device issues a rerun command and the master disconnects from the bus. Because a master operating on a different bus may not be identifiable by the slaves accessed by the master, it is possible that a master will be permitted to access a slave which has just completed a task delegated by a different master before the delegating master reconnects. The result is that data earmarked for the delegating master is now lost to it, leading to an erroneous result or system failure.